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MC74AC323 MC74ACT323
Advance Information
8 Input Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
The MC74AC323/74ACT323 is an 8-bit universal shift/storage register with 3-state outputs. Its function is similar to the MC74AC299/74ACT299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load. * * * * * * Common Parallel I/O for Reduced Pin Count Additional Serial Inputs and Outputs for Expansion Four Operating Modes: Shift Left, Shift Right, Load and Store 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 mA ACT323 Has TTL Compatible Inputs
VCC 20 S1 19 DS7 18 Q7 17 I/O7 16 I/O5 15 I/O3 14 I/O1 13 CP 12 DS0 11
8-INPUT UNIVERSAL SHIFT/ STORAGE REGISTER WITH SYNCHRONOUS RESET AND COMMON I/O PINS
N SUFFIX CASE 738-03 PLASTIC
DW SUFFIX CASE 751D-04 PLASTIC
1 S0
2 OE1
3 OE2
4 I/O6
5 I/O4
6 I/O2
7 I/O0
8 Q0
9 SR
10 GND
LOGIC SYMBOL
PIN NAMES CP DS0 DS7 S0, S1 SR OE1, OE2 I/O0-I/O7 Q0, Q7 Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Master Reset 3-State Output Enable Inputs Multipled Parallel Data Inputs or 3-State Parallel Data Outputs Serial Outputs S0 S1 CP
1 2
DS0
DS7 Q7
OE
SR Q0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
This document contains information on a new product. Specifications and information herein are subject to change without notice.
FACT DATA 5-1
MC74AC323 MC74ACT323
LOGIC DIAGRAM
DS7 Q7
CP DQ I/O7
CP DQ I/O6
CP DQ I/O5
CP DQ I/O4
CP DQ I/O3
CP DQ I/O2
CP DQ I/O1
CP DQ I/O0
S0
S1 DS0 SR CP Q0 OE1 OE2
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FACT DATA 5-2
MC74AC323 MC74ACT323
FUNCTIONAL DESCRIPTION
The MC74AC323/74ACT323 contains eight edgetriggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3 state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other TRUTH TABLE
Inputs Response SR L H H H H S1 X H L H L S0 X H H L L CP Synchronous Reset; Q0 - Q7 = LOW Parallel Load; I/On Qn Shift Right; DS0 Q0, Q0 Q1, etc. Shift Left; DS7 Q7, Q7 Q6, etc. Hold
X = Immaterial = LOW-to-HIGH Clock Transition
state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
X
H = HIGH Voltage Level L = LOW Voltage Level
MAXIMUM RATINGS*
Symbol VCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) AC Devices except Schmitt Inputs VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current -- High Output Current -- Low -40 25 VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 150 40 25 10 ns/V 8.0 140 85 -24 24 C C mA mA ns/V Typ 5.0 5.0 Max 6.0 5.5 VCC V Unit V
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA 5-3
MC74AC323 MC74ACT323
DC CHARACTERISTICS
74AC Symbol Parameter VCC (V) TA = +25C Typ VIH Minimum High Level Input Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOZT Maximum Input Leakage Current Maximum 3-State Current Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 0.002 0.001 0.001 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 74AC TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.6 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 6.0 75 -75 8.0 80 V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A V *VIN = VIL or VIH -12 mA IOH -24 mA -24 mA IOUT = 50 A V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V
V
A A mA mA A
5.5 5.5 5.5 5.5
IOLD IOHD ICC
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
FACT DATA 5-4
MC74AC323 MC74ACT323
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74AC Symbol Parameter VCC* (V) TA = +25C CL = 50 pF Min fmax tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Propagation Delay CP to I/On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Max 74AC TA = -40C to +85C CL = 50 pF Min Max MHz ns ns ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-7 3-8 3-7 3-8 Unit Fig. No.
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74AC Symbol Parameter VCC* (V) Typ ts th ts th ts th tw Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On, DS0, DS7 to CP Hold Time, HIGH or LOW I/On, DS0, DS7 to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP CP Pulse Width HIGH or LOW 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 TA = +25C CL = 50 pF 74AC TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-6
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
FACT DATA 5-5
MC74AC323 MC74ACT323
DC CHARACTERISTICS
74ACT Symbol Parameter VCC (V) TA = +25C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZT Maximum Input Leakage Current Maximum 3-State Current Additional Max. ICC/Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 0.001 0.001 1.5 1.5 1.5 1.5 4.49 5.49 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 0.6 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 6.0 1.5 75 -75 8.0 80 V V V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A *VIN = VIL or VIH -24 mA IOH -24 mA IOUT = 50 A *VIN = VIL or VIH 24 mA IOL 24 mA VI = VCC, GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
V
V
V
A A mA mA mA A
5.5 5.5 5.5 5.5 5.5 0.6
ICCT IOLD IOHD ICC
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
FACT DATA 5-6
MC74AC323 MC74ACT323
AC CHARACTERISTICS (For Figures and Waveforms -- See Section 3)
74ACT Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Propagation Delay CP to I/On Output Enable Time Output Enable Time Output Disable Time Output Disable Time 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 120 5.0 5.0 5.0 6.0 3.5 3.5 4.0 3.0 TA = +25C CL = 50 pF Typ 125 9.0 9.0 8.5 10 7.5 7.5 8.5 8.0 12.5 13.5 12.5 14.5 11 11.5 12.5 11.5 Max 74ACT TA = -40C to +85C CL = 50 pF Min 110 4.0 4.5 4.5 5.0 3.0 3.0 3.0 2.5 14 15 14.5 16 12.5 13 13.5 12.5 Max MHz ns ns ns ns ns ns ns ns 3-3 3-6 3-6 3-6 3-6 3-7 3-8 3-7 3-8 Unit Fig. No.
* Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74ACT Symbol Parameter VCC* (V) Typ ts th ts th ts th tw Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On, DS0, DS7 to CP Hold Time, HIGH or LOW I/On, DS0, DS7 to CP Setup Time, HIGH or LOW SR to CP Setup Time, HIGH or LOW SR to CP CP Pulse Width HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 5.0 2.0 0 1.0 0 1.0 0 2.0 TA = +25C CL = 50 pF 74ACT TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 5.0 1.5 4.0 1.0 2.5 1.0 4.0 5.0 1.5 4.5 1.0 2.5 1.0 4.5 ns ns ns ns ns ns ns 3-9 3-9 3-9 3-9 3-9 3-9 3-6
* Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 170 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
FACT DATA 5-7
MC74AC323 MC74ACT323
OUTLINE DIMENSIONS
N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
11
-A-
20
B
1 10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
20X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
18X SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029
G
K
M
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FACT DATA 5-8
*MC74AC323/D*
MC74AC323/D

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